1. Field of the Invention
The invention relates to a read only semiconductor memory device for reading information stored in a selected memory cell, by discharging or maintaining the electrical potentials of pre-charged bit lines.
2. Description of the Prior Art
A conventional read only semiconductor memory device (referred to as ROM below) reads out stored information (either logic "0" or logic "1"), by transferring or not the electrical potential of the bit lines connected to memory cells of the memory, that is, by discharging or maintaining the electrical potential of the bit lines.
The electrical potential is transferred according to the information stored in the memory cell. When transferring the electrical potential, a significant electrical power is consumed. A reduction of the electrical power consumption of a ROM is disclosed in the Laid-open Japanese patent publication Hei 8-161895. In this example, a ROM includes memory cells arranged in a plurality of rows and columns. When a memory cell stores information "0", the memory cell is made conductive between a bit line and a ground node. When a memory cell stores information "1", the memory cell maintains a non-conductive state between the bit line and the ground node. In this type of ROM, a control flag memory cell is provided for respective rows of the memory cells, and an EX-OR gate is provided for respective rows.
When the number of "0" 's included in one row exceeds a predetermined number, the data in the row are inverted and stored. When the number of "0" 's included in one row is smaller than the predetermined number, the data are stored without being inverted.
If the plurality of the memory cells arranged in one row store inverted data (converted information), the control flag memory cells corresponding to the row store the information "0", respectively. If the plurality of the memory cells arranged in one row store non-inverted data (non-converted information), the control flag memory cells corresponding to the row store the information "1", respectively.
The respective EX-OR gates produce an exclusive logical sum between the information read from the memory cells in the rows and the information read from the control flag memory corresponding to the row. The EX-OR gates output results of addition as information read from the memory cell arrangement. That is to say, when the information stored in the memory cells is inverted information, the EX-OR gates invert the information and output the result. When the information stored in the memory cells are non-inverted information, the EX-OR gates output the information without inverting.
In this manner, the number of "0" 's stored in the memory cells is reduced. By reducing the number of stored "0" 's, less electrical potential is transferred from the bit lines when the information is read from the memory cells. As a result, power consumption is also reduced.
In addition, power consumption may be reduced by dividing the memory cells into a plurality of blocks in the row direction, and by providing a control flag memory cell for corresponding blocks.
However, in the above-mentioned ROM, since the EX-OR gates are provided for every row, the size of the surrounding circuit other than the memory cell array becomes large. Moreover, since the EX-OR gates are too large to be placed between the bit lines, it takes a large area to place the EX-OR gates on the semiconductor substrate. This occupation of the large area prevents large scale integration of a semiconductor circuit.